رقم الجزء 93000065-01

معلومات الجزء
160 mhz, two slot, c size, vxibus register based module; contains: timebase, timing generators, trigger circuits, wait-for-condition circuit, end-if-ready circuits, marker circuits and sequencer, provides 12 pattern clocks, power requirements: p5v: 1.6a peak, 80ma dynamic; m5.2v: 8.9a peak, 150 ma dynamic; m2v: 5.9a, 150ma dyn; timing cycle duration: 50 ns or 4 subcycles (whichever is greater)/1024 subcycles; resolution: 1 subcycle; subcycle period: min-6.25 ns/max-409.6 us; resolution: 6.25 ns; accuracy: 0.01 pct.; up to 256 timing cycles, nte 1024 subcycles; stimulus pattern clock delay: min-0 subcycle/max-timing cycle duration-1 subcycle, resolution: 1 subcycle; output levels: max. Continuous output current: porm 24 ma per line; high-open circuit: 4.4 v min.; low-open circuit: 0.1 v max; output impedance 50 ohms; capacitance: lt 20 pf; operating temp: 0-55 deg. C