رقم الجزء A-A-58042

معلومات الجزء
32 data channel inputs; operates from internal (asynchronously to events in uut) and external (synchronous) clocks; 2 clock qualifier inputs which can be logically combined to qualify data acquisition in synchro operation; data inputs samples asynchronously at 100 mega samples per sec and synchronously at up to 25 mega samples per sec; crt display; logic threshold selection accuracy greater than porm 5pct of threshold porm 5 pct of total variable voltage range; data set up time less than 12 nsec before active clock transition; data hold time less than 2 nsec; wide range microprocessor and bus support options; integrated state/timing trigger resources; glitch capture down to 3 nsecs; simultaneous 200 mhz timing/50 mhz state on all channels; includes probes, leads, power cord, & operation manuals